1. Field of the Invention
The present invention relates to memory devices and, more particularly, to non-volatile latches that operate as memory devices.
2. Description of the Related Art
Semiconductor memories are well known and can be classified as either volatile or non-volatile memory. Volatile memory loses stored information (data) once power is removed, while non-volatile memory retains its stored information even after power is removed.
One common type of semiconductor memory that is non-volatile is known as a non-volatile latch. A single non-volatile latch provides information storage for one-bit of data through use of a pair of cross-coupled drive transistors which each have a load. The load for each of the drive transistors is typically a transistor but can also be a non-active device such as a resistor. Non-volatile latches also provide a continuous status output signal and thus do not require read amplifiers or refresh operations.
FIG. 1 is a schematic diagram of a conventional non-volatile latch circuit 100. The non-volatile latch circuit 100 is a complementary metal-oxide-semiconductor (CMOS) circuit having n-type metal-oxide-semiconductor (NMOS) devices and p-type metal-oxide-semiconductor (PMOS) devices. The non-volatile memory circuit 100 includes a first floating-gate NMOS transistor 101 and a second floating-gate NMOS transistor 102. The NMOS transistor 101 and the second NMOS transistor 102 each operate as a memory cell. The non-volatile memory circuit 100 also includes a first PMOS transistor 104 and a second PMOS transistor 106. The first PMOS transistor 104 serves as a load for the first floating-gate NMOS transistor 101, and the second PMOS transistor 106 serves as a load for the second floating-gate NMOS transistor 102. Additionally, the non-volatile latch circuit 100 may also include an inverter 108 to buffer the data stored in the non-volatile latch and thus provide a voltage output (V.sub.OUT) for the memory bit.
Conventional non-volatile latches are programmed to store data and then retain the data until subsequently reprogrammed or cleared. Unfortunately, however, when programming is weak or leakage currents are present, non-volatile latches are significantly more likely to fail and thus lose the stored data. Although the programming of stored data can be verified after programming in a digital sense (i.e., "0" or "1"), conventionally there exists no way to conveniently examine program strength (e.g., program charge) of non-volatile latches. As a result, non-volatile latches with weak programming or significant leakage currents are normally not identified and thus used without knowledge of being susceptive to failure.
Thus, there is a need for improved approaches to examining program strength of non-volatile latches.